JP-A-2001-196573 discloses a semiconductor device having a semiconductor region inserted in a trench. Regarding a method for manufacturing a semiconductor device, a first epitaxial layer is grown onto a silicon substrate including the trench by epitaxial growth. A portion of the first epitaxial layer corresponding to an opening of the trench is etched by an HCl gas. Then, a second epitaxial layer is grown onto the first epitaxial layer.
JP-A-2001-274398 discloses a three-dimension power MOSFET in which an N− type drift layer, a P type channel layer and an N+ type source layer (hereinafter referred to as a three-layered configuration) are formed into a trench formed on a silicon substrate. When the configuration disclosed in JP-A-2001-274398 is applied to the method disclosed in JP-A-2001-196573 and the three-layered configuration is formed in the trench, the P type channel layer is liable to form a thin layer at a bottom portion of the trench.
For example, as shown in FIG. 22A, an N− type layer J3 is formed onto the silicon substrate J1 including the trench J2 by epitaxial growth after the trench J2 is formed on the silicon substrate J1. A surface portion of the N− type layer J3 is then removed by HCl gas. Thus, an opening portion of the N− type layer J3 is enlarged as shown in FIG. 22B. The N− type layer J3 is grown again, and a P type layer J4 and an N+ type layer J5 are grown onto the N− type layer J3 as shown in FIG. 22C. Thereafter, the silicon substrate J1 configured above is heated to 1150° C. for 10 minutes. As a result, the three-layered configuration (J3–J5) shown in FIG. 22D is completed. Upon SCM analysis performed on the silicon substrate with the three-layered configuration, a portion of the P type layer (P type channel layer) J4 located at the bottom portion of the trench J2 is transformed into an N type layer. Accordingly, the N+ source layer and the N− type drift layer are electrically connected one another, increasing a leak current when the three-dimensional MOSFET is OFF and decreasing a withstanding voltage of a drain region that approximately equals a withstanding voltage of a source region.